The present invention relates generally to a high frequency digital signal receiver, and more particularly to a digital signal receiver that uses integration techniques to reduce latency of signals on a bus.
An efficient high speed signaling system requires the use of well-controlled waveforms. For example, in a high speed signaling system with a clock cycle time in the range of approximately one to two nanoseconds, the amplitude of the voltage swing, the rise and fall times, and the duty cycle of the signaling waveform should be within well-defined limits. The term xe2x80x9cvoltage swingxe2x80x9d refers to a difference between a minimum predetermined voltage and a maximum predetermined voltage of a signal. For example, typical limits may include a voltage swing of approximately one volt, a near fifty percent duty cycle, and a rise and a fall time of approximately one hundred picoseconds (ps). In some systems, the voltage swing of CMOS signals ranges from a low of zero volts to a high of five volts. In other systems, the voltage swing of the CMOS signals ranges from a low of zero volts to a high of 2.5 volts.
A receiver system that receives and converts the high-speed, low swing waveforms to CMOS signals requires careful design, especially when multiple high-speed waveforms are received simultaneously and where noise is a significant factor.
The following naming convention will be used for signals. For example, the name xe2x80x9csystem clockxe2x80x9d will refer to one signal, while that signal""s complement will be referred to as xe2x80x9csystem clock Bxe2x80x9d or xe2x80x9csystem clock_b.xe2x80x9d In other words, the complement of a signal will have an upper or lower case xe2x80x9cbxe2x80x9d following its name.
As shown in FIG. 1, a prior art sampling receiver 100 has a sense-amplifier 102 and a latch 104. The sense amplifier 102 receives, senses and amplifies small changes in the input signal, Data In, with respect to a reference voltage Vref, and outputs a differential signal, A and A_b. The latch 104 amplifies, stores and converts the differential signal, A and A_b, to predetermined low and high values.
Referring also to the timing diagram of FIG. 2, a system clock and its complement, system clock_b, control the operation of the sampling receiver 100. When system clock_b is transitions low the sense amplifier 102 is disabled. Two linear load/precharge transistors 112, 114 become active and pull signals A and A_b at nodes NA and NAxe2x80x94b to a high voltage level.
When system clock_b transitions high, the sense amplifier 102 is enabled and senses the voltage of the data input signal, Data In. The two linear load transistors 112, 114 become inactive. When the voltage of the data input signal, Data In, at the gate of input transistor 116 exceeds the reference voltage VREF at the gate of transistor 118, the input transistor 116 becomes active and pulls output signal A_b to a low voltage level via a current sink 120. When the data input signal is less than or equal to the reference voltage VREF, the input transistor 116 is inactive (i.e., or at least less conductive than transistor 118) and the output signal A_b remains high.
The cross-coupled transistor pair 122, 124 stores the state of signals A and A_b. Initially, when system clock_b is low, transistors 112 and 114 are enabled and act as linear load devices to the differential pair 116, 118. When system clock_b transitions high, transistors 112 and 114 become inactive and the cross-coupled pair 122, 124 is enabled to sense and amplify variations of the input data signal, Data In. When the voltage of the input signal, Data In, is less than the reference voltage VREF, transistor 118 is active and pulls the voltage of signal A at node NA to ground, which causes the voltage of signal A_b at node NAxe2x80x94b to transition high. When the voltage of the input signal Data In exceeds the reference voltage VREF, transistor 116 becomes active and pulls the signal A_b at node NAxe2x80x94b low; in addition, transistor 118 becomes inactive and the signal A_b at node NAxe2x80x94b is pulled high. The cross-coupled pair 122, 124 acts as an amplifier for small changes in the voltage of the input signal Data In with respect to the reference voltage VREF.
When system clock_b transitions low, sense amplifier 102 is disabled and the complementary output signals A and A_b from the sense amplifier 102 are stored in latch 104. Latch 104 is enabled by the system clock.
In latch 104, an equalizing transistor 126 becomes active when the system clock transitions low and drives the output signals Out and Out_b to the same voltage level. When the system clock transitions high, the equalizing transistor 126 becomes inactive, latch-enable transistors 128, 130 become active and enable the latch-data-input transistors 132, 134 to act as a pull-down circuit when responding to the differential output signals A and A_b from the sense amplifier 102. In particular, when the system clock is high, the latch-data-input transistors 132, 134 are responsive to the amplified signals A and A_b. A four transistor latch circuit 136 latches the associated state of signals A and A_b, and generates the latched-output signals, Out 142 and Out_b 144. The four transistor latch circuit 136 includes transistors 152, 154, 156 and 158.
When the system clock transitions low, latch-enable transistors 128, 130 become inactive thereby causing the latch 104 to become non-responsive to signals A and A_b. In this way, the latch 104 captures the state of A and A_b at the high-to-low transition of the system clock. To reduce the probability of errors caused by noise, the timing of the high-to-low transition of the system clock should occur at a time when the differential amplitude between the A and A_b signals is greatest. In addition, when a system has multiple receivers and drivers operating simultaneously, the likelihood of noise injection on VREF and, consequently, errors is increased.
The circuit of FIG. 2 senses even data values, D0 and D2, in response to the falling edge of the system clock, and latches the even data values in response to the rising edge of the system clock. Another circuit, similar to the circuit of FIG. 2, operates on opposite clock edges senses and latches odd data values (e.g., sensing in response to the rising edge of the system clock) and latching in response to the falling edge of the system clock.
In FIG. 3A, an integrating receiver 180 improves performance in a noisy environment. The integrating receiver 180 is a type of matched filter. In the integrating receiver 180, an integrator 182, a sample-and-hold (S/H) circuit 184, an amplifier 186 and a latch 188 are connected in series and receive and output differential signals. The integrating receiver 180 integrates a bias current IBIAS1 based on the difference between the differential input signals VIN+ and VINxe2x88x92 over a given period of time, called the integration interval. Prior to the start of the integration interval, the output value of the integrator 182 is initially set equal to zero volts. After integration is complete and additional processing, the latch 188 stores the result of the integration.
Referring also to FIG. 3B, the integrating receiver 180 operates according to three phasesxe2x80x94an integration phase (Phase I), a hold phase (Phase II) and a latch phase (Phase III). A first timing signal xcfx86 192 and a second timing signal xcexa8_b 194 define the phases and control the operation of the integrating receiver 180. The first timing signal xcfx86 defines the integration interval or phase and is a clock that operates at the system clock frequency. The second timing signal xcexa8_b defines the hold and latch phases when the first timing signal xcfx86 is no longer in the integration phase. In some implementations, the first timing signal xcfx86 is phase shifted with respect to the system clock.
During Phase I, the integration interval, when the first timing signal xcfx86 is high, the integrator 182 receives differential input signals VIN+ 196 and VINxe2x88x92 198. The integrator 182 integrates a predetermined amount of current based on the polarity of the data input signals VIN+ 196 and VINxe2x88x92 198 and generates a differential integrated signal. The sample-and-hold circuit 184 receives the differential integrated signal output by the integrator 182, and the latch 188 is held in a reset state.
During Phase II, when the first timing signal xcfx86 and the second timing signal xcexa8_b are low, the sample-and-hold circuit 184 samples and holds the state of the differential output signal from the integrator 182. The amplifier 186 also amplifies the output of the sample-and-hold circuit 184 and generates an amplified signal.
During Phase III, when the second timing signal xcexa8_b is high and the first timing signal xcfx86 is low, the amplified signal is captured in the latch 188. The integrator 182 and the sample-and-hold circuit 184 are reset to receive the next differential data bit.
One important metric of the integrating receiver is its overall delay or latency, referred to herein as the input-to-output latency. The input-to-output latency is measured from the time when the data input signals VIN+ 196 and VINxe2x88x92 198 are validly present at the integrator input to the time when the captured signal is validly present at the output of the latch 188. In high-speed signaling systems and, in particular, in memory systems, the input-to-output latency should be as small as possible.
In FIG. 4, the integrator 182 and the sample and hold circuit 184 of FIG. 3 are shown in more detail. Integration occurs on nodes NINTA 202 and NINTB 204, with the capacitance of these nodes being determined by the inherent capacitance of the transistors coupled to them. In the integrator 182, a first current steering circuit 210 receives a bias current IBIAS from a current source 212 and steers the bias current IBIAS to either integration node NINTA 202 or NINTB 204 based on the differential input signal, VIN+ and VINxe2x88x92. The current source 212 includes a PMOS transistor M3 214 that supplies the bias current IBIAS in response to a bias voltage VBIAS applied to the gate of transistor 214. In the current steering circuit 210, a first differential input pair, transistors M1 206 and M2 208, receives the differential input signal VIN+ and VINxe2x88x92, respectively. When VINxe2x88x92 is at a low voltage level, transistor M1 206 steers the bias current IBIAS to node NINTA 202, thereby charging node NINTA and increasing the voltage VINT+ at node NINTA. When VIN+ is at a low voltage level, transistor M2 208 steers the bias current IBIAS to node NINTB, thereby charging node NINTB and increasing the voltage VINTxe2x88x92 at node NINTB.
A compensating integration circuit 222 eliminates a source of error in the integrator 182 caused primarily by the gate to drain capacitance of transistors M1 206 and M2 208. In the compensating integration circuit 222, a second differential input pair, transistors MC1 224 and MC2 226, receives the differential input signals VIN+ 206 and VINxe2x88x92 208, respectively, and, functions as a current steering circuit to steer compensating bias current IBIASC towards the integration nodes NINTA and NINTB. A compensating current source, PMOS transistor MC3 228, provides the compensating bias current IBIASC. The amount of current IBIASC supplied by the compensating current source is also determined by the bias voltage VBIAS. Transistor MC4 230 pulls up the voltage at node tailc to the power supply voltage VDD.
An integrator reset circuit 240 resets the integrator 182 by removing any charge from the integration nodes NINTA and NINTB prior to integrating. The integrator 182 is reset during Phase III when xcfx86_b and xcexa8_b are high.
One disadvantage of this integrator 182 is that its input common-mode range is limited. The common mode of differential signals VIN+ and VINxe2x88x92 is the average value of the two signals. The input common mode range is low in order that the first current steering circuit 210 can fully steer the integrating current IBIAS and operate at a sufficiently high conductance to keep the PMOS current source transistor M3 214 in saturation. A low input common mode range limits the types of drivers and termination networks which may be used. Therefore, an integrator 182 with an increased input common mode range is desirable.
Another disadvantage is that the integrator 182 has a low voltage gain when either transistor 206 or 208 of the differential pair does not fully steer the current IBIAS to either of the integration nodes NINTA and NINTB. The low voltage gain Av of the integrator 182 is determined by the following relationship:
xe2x80x83Av=((VINT+)xe2x88x92(VINTxe2x88x92))/((VIN+)xe2x88x92(VINxe2x88x92)).xe2x80x83xe2x80x83(1)
Because of the low voltage gain Av, the integrator 182 may require large input voltage swings to fully steer the current IBIAS from the current source 214. Therefore, an integrator 182 that fully steers current smaller changes in the input voltage is also desirable.
The sample and hold circuit 184 (FIG. 4) provides the differential integrated voltages, VINT+ and VINTxe2x88x92, from the integrator 182 to the sense amplifier and latch, as sample output voltages, VO+ and VOxe2x88x92. In the sample and hold circuit 184, transistors S1250 and S2252 are connected in series to the integration nodes NINTA and NINTB, 202 and 204, respectively. The first timing signal xcfx86 is supplied to the gates of transistors S1250 and S2252, respectively. During Phase I, when the first timing signal xcfx86 is high, the differential voltage, VINT+ and VINTxe2x88x92, on the integration nodes, NINTA+ and NINTBxe2x88x92, is output by the sample and hold circuit 184 as VO+ and VOxe2x88x92. During Phase II, when xcfx86 is low, transistors S1250 and S2252 are inactive and the sampled voltages, VO+ and VOxe2x88x92, remain on sampling nodes NSAMPA 260 and NSAMPB 262, respectively, because of the inherent capacitance of the sample and hold circuit 184. During Phase III, a reset circuit 254 drives the sample output voltage VO+ and VOxe2x88x92 on nodes, NSAMPA 260 and NSAMPB 262, respectively, to circuit ground to reset the sample and hold circuit 184.
FIG. 5 is a circuit diagram of the amplifier 186 and latch 188 of FIG. 3. The amplifier 186 amplifies the differential output of the sample-and-hold circuit, VO+ and VOxe2x88x92, to generate amplified signals VA+ and VAxe2x88x92, respectively, during Phases II and III. An amplifier current source 270, PMOS transistor 272, supplies an amplifier bias current IBIASA to a differential PMOS pair, transistors 274 and 276 in response to the bias voltage VBIAS. The bias voltage VBIAS is sufficiently low with respect to the supply voltage to operate PMOS transistor 272 in the saturation region.
An amplifier equalizing transistor 278 becomes active during Phase I, when the first timing signal xcfx86 is high, to equalize the outputs, VA+ and VAxe2x88x92, of the amplifier 186 such that the amplifier 186 outputs no differential voltage. During Phases II and III, when the first timing signal xcfx86 is low, the equalizing transistor 278 is inactive.
An amplifier load circuit 280 pulls one of the amplifier outputs, VA+ and VAxe2x88x92, to ground when either of the input voltages VO+ or VOxe2x88x92 is sufficiently low to cause one of the PMOS transistors, 276 or 274, respectively, to become active. In the amplifier load circuit 280, NMOS transistor pairs 282, 284 connect to the transistors of amplifier differential pair 274, 276, respectively. The NMOS transistor pairs 282, 284 are cross-coupled such that, for example, when the amplifier output voltage VA+ is high, NMOS transistor pair 284 is inactive and NMOS transistor pair 282 is active and pulls VAxe2x88x92 low. Each NMOS transistor pair 282, 284 includes two NMOS transistors, 286 and 288, 292 and 294, respectively, connected in parallel.
Operating PMOS transistor 272 as a current source provides high gain-bandwidth for the latch 188 and reduces propagation delay. However, supplying the amplifier bias current IBIASA in this way causes the amplifier 186 to consume static direct current and therefore static power. Static power is that power constantly being consumed by a circuit, regardless of its mode or data. Because the amplifier 186 consumes a significant amount of static power, the amplifier 186 may be unsuitable for use in devices that use a large number of receivers. Therefore an amplifier for use in a receiver that reduces static power consumption is desirable.
The latch 188 is reset during Phases I and II, and stores the output of the amplifier 186 during Phase III. During Phases I and II, when xcexa8_b is low, a latch-load-circuit that includes PMOS transistors 302 and 304, precharges the differential latch output, VL+ and VLxe2x88x92, to the supply voltage. Also during Phases I and II, a latch output equalizing transistor 306 becomes active and causes the differential latch output VL+ and VLxe2x88x92 signals to be the same.
During Phase III, when xcexa8_b is high, the latch-load-circuit and the latch output equalizing transistor 306 become inactive. A latch-input pair, NMOS transistors 308 and 310, receives the differential output of the amplifier 186. A first cross-coupled pair, transistors 312, 314, latches the state of the amplifier output signals, VA+ and VAxe2x88x92. Pass transistors 316, 318 are active and supply the output of the first cross-coupled pair 312, 314 as differential latch output signals, VL+ and VLxe2x88x92. A second cross-coupled pair, transistors 320, 322, latches the state of the differential latch output signals, VL+ and VLxe2x88x92, to improve the gain of the latch.
The output of the latch 188, and therefore the output of the integrating receiver 180, is valid after the beginning of Phase III. The input-to-output latency of the integrating receiver 180 is equal to the duration of Phase I plus the duration of Phase II plus the duration of the latch output delay from the beginning of Phase III. Therefore, the input-to-output latency consumes a significant portion of the system clock period. In particular, the input-to-output latency consumes a large amount of time relative to a typical clock cycle time of approximately two nanoseconds (ns) for high speed signaling systems, and potentially limits the performance of the system in which the integrating receiver is used. Therefore, an integrating receiver with reduced input-to-output latency is desirable.
In a receiver, an integrator generates integrated signals based on input signals, and a sense amplifier samples and converts the integrated signals to a logic signal. The combination of the integrator and sense amplifier reduces the input-to-output latency from the time when an input signal is valid to when the output of the sense amplifier is valid. This receiver has low static power consumption and a wide input common mode range.
In particular, the receiver accumulates a charge to produce an output voltage during an integration time interval in accordance with a data input signal, samples the output voltage and holds and converts the sampled voltage into a logic signal such that the logic signal represents the polarity of the data input signal. The input-to-output latency is defined as the time from when the data input signal is valid to when the logic signal is valid. This input-to-output latency is approximately equal to the integration time plus the time to convert the sampled voltage. The input-to-output latency is lower than the input-to-output latency of the prior art receivers described above; and therefore improves system performance.
In one aspect of the invention, a preamplifier conditions the input signal and provides the conditioned input signal to the integrator.
In another aspect of the invention, rather than using an integrator, a preamplifier is connected to a sense amplifier that incorporates an integration function.
In a system having multiple receivers, each receiver receives adjusted timing signals to compensate for skew in the received signals. In an alternate embodiment, the receivers have an equalization circuit to compensate for intersymbol interference. In another aspect of the invention, an offset cancellation circuit removes any manufacturing induced voltage offsets from mismatched devices in the receiver. In yet another aspect of the invention, a multi-phased receiver system uses multiple receivers to increase bus speed.
A memory device incorporates the integrating receiver of the present invention.